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W26L010A 64K x 16 HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W26L010A is a high-speed, low-power CMOS static RAM organized as 65,536 x 16 bits that operates on a single 3.3-volt power supply. This device is manufactured using Winbond's high performance CMOS technology. The W26L010A has an active low chip select, separate upper and lower byte selects, and a fast output enable. No clock or refreshing is required. Separate byte select controls ( LB and UB ) allow individual bytes to be written and read. LB controls I/O1-I/O8, the lower byte. UB controls I/O9- I/O16, the upper byte. This device is well suited for use in high-density, high-speed system applications.
FEATURES
* High speed access time: 10/12 nS (max.) * Low power consumption: * Single +3.3V power supply * Fully static operation
-
Active: 530 mW (max.)
* All inputs and outputs directly TTL compatible * Three-state outputs * Data byte control * Available packages: 44-pin 400 mil SOJ and
- LB (I/O1-I/O8), UB (I/O9-I/O16)
- No clock or refreshing
44-pin TSOP(II)
PIN CONFIGURATION
BLOCK DIAGRAM
VDD VSS A0 . . DECODER
A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VDD VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-PIN
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A15 A14 A13 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VDD I/O12 I/O11 I/O10 I/O9 NC A12 A11 A10 A9 NC
A15
CORE ARRAY
UB CS OE WE LB
CONTROL DATA I/O I/O1 . . I/O16
PIN DESCRIPTION
SYMBOL A0-A15 I/O1-I/O16 CS WE OE LB UB VDD VSS NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Input Output Enable Input Lower Byte Select I/O1-I/O8 Upper Byte Select I/O9-I/O16 Power Supply Ground No Connection
-1-
Publication Release Date: July 1998 Revision A3
W26L010A
TRUTH TABLE
CS
OE
X H L L L X X X X
WE
LB
UB
X X L H L L H L H
MODE Not Selected Output Disable 2 Bytes Read Lower Byte Read Upper Byte Read 2 Bytes Write Lower Byte Write Upper Byte Write Output Disable
I/O1-I/O8 High Z High Z DOUT DOUT High Z DIN DIN High Z High Z
I/O9-I/O16 High Z High Z DOUT High Z DOUT DIN High Z DIN High Z
VDD CURRENT ISB, ISB1 IDD IDD IDD IDD IDD IDD IDD IDD
H L L L L L L L L
X H H H H L L L X
X X L L H L L H H
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to +4.6 -0.5 to VDD +0.5 1.5 -65 to +150 0 to +70 UNIT V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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W26L010A
Operating Characteristics
(VDD = 3.3V 5%, VSS = 0V, TA = 0 to 70 C)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current
SYM. VIL VIH ILI ILO
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD Output Pins in High Z, See Truth Table IOL = +8.0 mA IOH = -4.0 mA CS = VIL (max.), Cycle = min. I/O = open, Duty = 100% 10 12
MIN. -0.5 +2.0 -10 -10
TYP. -
MAX. +0.8 VDD +0.3 +10 +10
UNIT V V A A
VOL VOH IDD
2.4 -
-
0.4 160 140 30 10
V V mA
ISB ISB1
CS = VIH (min.), Cycle = min. CS = VDD -0.2V, I/O = open All other pins = VDD -0.2V/GND
mA mA
Note: Typical characteristics are evaluated at VDD = 3.3V, TA = 25 C.
CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 8
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 2 nS 1.5V CL = 30 pF, IOH/IOL = -4 mA/8 mA CONDITIONS
-3-
Publication Release Date: July 1998 Revision A3
W26L010A
AC Test Loads and Waveform
R1 320 ohm R1 320 ohm 3.3V OUTPUT OUTPUT 30 pF Including Jig and Scope R2 350 ohm 5 pF Including Jig and Scope R2 350 ohm 3.3V
( For TCLZ, TBLZ, TOLZ, TCHZ, TBHZ, TOHZ, TWHZ, TOW )
3.0V
90% 10% 2 nS 10%
90%
0V
2 nS
(VDD = 3.3V 5%, VSS = 0V, TA = 0 to 70 C)
(1) Read Cycle
PARAMETER SYM.
W26L010A-10 W26L010A-12
UNIT
MIN. Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid UB , LB Access Time Output Hold from Address Change Chip Select to Output in Low Z Chip Deselect to Output in High Z Output Enable to Output in Low Z Output Disable to Output in High Z UB , LB Select to Output in Low Z
UB , LB Deselect to Output in High Z
These parameters are sampled but not 100% tested.
MAX. 10 10 5 5 - - 5 - 5 - 5
MIN. 12 - - - - 3 3 - 0 - 0 -
MAX. 12 12 6 6 - - 6 - 6 - 6 nS nS nS nS nS nS nS nS nS nS nS nS
TRC TAA TACS TOE TBA TOH TCLZ* TCHZ* TOLZ* TOHZ* TBLZ* TBHZ*
10 - - - - 3 3 - 0 - 0 -
-4-
W26L010A
AC Characteristics, continued
(2) Write Cycle
PARAMETER SYM.
W26L010A-10 W26L010A-12
UNIT
MIN. Write Cycle Time Chip Select to End of Write Address Valid to End of Write Address Setup Time UB , LB Select to End of Write Write Pulse Width Write Recovery Time CS , WE TWC TCW TAW TAS TBW TWP TWR TDW TDH TWHZ* TOW* 10 9 9 0 9 9 0 6 0 - 3
MAX. - - - - - - - - - 6 -
MIN. 12 10 10 0 10 10 0 7 0 - 3
MAX. - - - - - - - - - 7 - nS nS nS nS nS nS nS nS nS nS nS
Data Valid to End of Write Data Hold from End of Write Write to Output in High Z End of Write to Output Active
These parameters are sampled but not 100% tested.
-5-
Publication Release Date: July 1998 Revision A3
W26L010A
Timing Waveforms Read Cycle 1
(Address Controlled,
CS
=
OE
=
UB
=
LB
= VIL,
WE
TRC
= VIH)
Address
TOH TAA TOH
DOUT
Read Cycle 2
(Chip Select Controlled,
OE
= VIL,
WE
= VIH)
TRC
Address
CS TACS T CLZ OE TOE TBA UB / LB TBHZ HIGH-Z D OUT T BLZ HIGH-Z TOHZ T CHZ
TOLZ
Notes: 1. WE is high for read cycle. 2. Device is continuously selected. CS = OE = LB = Low CS = OE = LB = Low 3. Address valid prior to or coincident with CS transition low.
-6-
W26L010A
Timing Waveforms, continued
Read Cycle 3
(Output Enable Controlled,
CS
=
UB
=
LB
= VIL,
WE
= VIH)
TRC Address TAA OE TAOE TOLZ DOUT TOH TOHZ
Write Cycle 1
(OE Clock)
T WC Address TWR OE TCW
CS
UB/LB TAW WE TAS D OUT
TBW
TWP
TDW D IN
TDH
-7-
Publication Release Date: July 1998 Revision A3
W26L010A
Timing Waveforms, continued
Write Cycle 2
(OE = VIL Fixed)
TWC Address TCW CS TBW UB/LB TAW WE TAS TWP TWHZ (1, 4) D OUT TDW D IN TDH TOH (2) TOW (3) TWR
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 10 12 10 12 OPERATING CURRENT MAX. (mA) 160 140 160 140 STANDBY CURRENT MAX. (mA) 10 10 10 10 PACKAGE
W26L010AJ-10 W26L010AJ-12 W26L010AT-10 W26L010AT-12
Notes:
44-pin 400 mil SOJ 44-pin 400 mil SOJ 44-pin TSOP 44-pin TSOP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
-8-
W26L010A
PACKAGE DIMENSIONS
44-pin Small Outline J Band
Dimension in inches
Dimension in mm Min. Nom. Max. 3.759
Symbol
44 23
Min. 0.128 0.025
Nom. 0.138
Max. 0.148
E
HE
1
22
A A1 A2 b1 b c D E e e1 HE L S y
3.251 3.585 0.635
0.105 0.110 0.026 0.028 0.015 0.007 1.120 1.125 0.395 0.400 0.044
0.115 0.032 0.020 0.013 1.130 0.405
2.41 0.66 0.381 0.178
2.54 0.711
2.67 0.813 0.508 0.330 28.70 10.29 1.42
28.45 28.58 10.03 1.12 10.16 1.27 9.40 11.05 2.06 11.18
0.050 0.056 0.37
D c A2 s Seating Plane b b1 e A L A1 y e1
0.435 0.082
0.440 0.445
11.30
0.045 0.004 0 10 0
1.14 0.10 10
44-pin Standard Type Two TSOP
Y
Dimension in inches
Dimension in mm Nom. Max. 1.20 0.05 1.00 0.35 0.15 1.05 0.45 0.17
Symbol
D A A2
Min.
Nom. Max. Min. 0.047
A1
A A1 A2 b c D E
0.002
0.037 0.039 0.041 0.95 0.010 0.014 0.018 0.25
H
D
E
0.005 0.006 0.007 0.12
0.721 0.725 0.729 18.31 18.41 18.51 0.396 0.400 0.404 10.06 10.16 10.26 0.455 0.463 0.471 11.56 11.76 11.96 0.031 0.016 0.020 0.024 0.031 0.004
o o o
L1
L
e
M
0.10 (0.004)
b
c
HD e L L1 Y
0.80 0.40 0.50 0.80 0.10
o
0.60
0
5
0
5
-9-
Publication Release Date: July 1998 Revision A3
W26L010A
VERSION HISTORY
VERSION A1 A2 DATE May 1995 Feb. 1998 1, 8, 9 6, 7 A3 Jul. 1998 3, 4 PAGE Initial Issued 1, 3, 4, 5, 8 Change the relative specification from 15/20 nS to 10/12 nS Add TSOP package Modify timing waveforms Revise Vcc from 3.3V 10% to 3.3V 5% DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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